Department of Computer Science University of San Francisco

Computer Science 315-01
Computer Architecture

Spring 2016

Class: MWF 11:45-12:50, LS G12
Lab: W 2:15-3:20, LS G12

Professor: Peter Pacheco
Office: Harney 540
Phone: 422-6630
Email: domain:, user: peter
Office Hours: MW 4:45-5:45, F 2:15-3:15, and by appointment

TA: Raul Montoya
Email: domain:, user: ramontoya
Office Hours: Th 3-4, F 3:30-4:30 Harney labs

Class mailing list: You will be automatically subscribed to the class mailing list. Please note that this list uses your USF email address. If you ordinarily read your email using another account, be sure to forward your USF email to the other account.

Course Syllabus (Here's a PDF Version.)

Homework Assignments

Code Examples

Other Information

  1. David Patterson's article, ``The Trouble with Multicore''
  2. Moore's Law and Transistor Counts from Wikipedia.
  3. Table showing relation between processor utilization and power consumption taken from the fourth edition of Patterson-Hennessy.
  4. The website for the MARS MIPS simulator
  5. The website for the QtSpim MIPS simulator.
  6. The MIPS Green Sheet, which has MIPS assembly instructions, instruction formats, registers, etc.
  7. The SPIM system calls. These are also available in MARS.
  8. List of possible topics for the first midterm.
  9. A key to the first midterm.
  10. Some pipeline diagrams for a 4-stage pipeline with different assumptions about the execution time of the stages:
    1. All the stages take 1 unit of time.
    2. All the stages take 1 unit of time except stage 2 which takes 2 units.
    3. Stages 1 and 4 take 1 unit of time, stage 2 takes 2, and stage 3 takes 3.
  11. List of possible topics for the second midterm.
  12. A key to the second midterm.
  13. Memory access time and cost in 2012
  14. Additional topics for the final exam

Peter Pacheco 2016-05-10